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Question Booklet Code: C Duration: 2 Hours
Course: Diploma Engineering in Computer Science Year: Third Year
Paper Code: 702305 Paper Name: Microprocessor
Attempt all below mentioned questions:
1. The minimum number of transistors
required to implement a two input AND
gate is
a. 2
b. 4
c. 6
d. 8
2. Using DeMorgan's Theorem we can
convert any AND-OR structure into
a. NAND-NAND
b. OR-NAND
c. NAND-NOR
d. NOR-NAND
3. For a memory with a 16-bit address
space, the addressability is
a. 16 bits
b. 8 bits
c. 2^16 bits
d. Cannot be determined
4. Because we wish to allow each ASCII
code to occupy one location in memory,
most memories are _____ addressable.
a. BYTE
b. NIBBLE
c. WORD (16 bits)
d. DOUBLEWORD (32 bits)
5. Circuit A is a 1-bit adder; circuit B is a 1
bit multiplier.
a. Circuit A has more gates than circuit B
b. Circuit B has more gates than circuit A
c. Circuit A has the same number of gates as
circuit B
d. None of the above
6. When the write enable input is not
asserted, the gated D latch ______ its
output.
a. can not change
b. clears
c. sets
d. complements
7. A structure that stores a number of bits
taken "together as a unit" is a
a. gate
b. mux
c. decoder
d. register
8. We say that a set of gates is logically
complete if we can build any circuit
without using any other kind of gates.
Which of the following sets are logically
complete
a. set of {AND,OR}
b. set of {EXOR, NOT}
c. set of {AND,OR,NOT}
d. None of the above
9. Of the following circuits, the one which
involves storage is
a. RS Latch
b. mux
c. nand
d. decoder
10. If the number of address bits in a
memory is reduced by 2 and the
addressability is doubled, the size of the
memory (i.e., the number of bits stored in
the memory)
a. doubles
b. remains unchanged
c. halves
d. increases by 2^(address bits)/addressability
CMJ UNIVERSITY, SHILLONG
TERM END EXAMINATION - 2013
2 | P a g e Centre for Collaboration of Industry and Institutions (CCII) – www.cmju.in
11. When memory read or I/O read are
active data is to the processor:
a. Input
b. Output
c. Processor
d. None of these
12. If m is a power of 2, the number of
select lines required for an m-input mux is:
a. m
b. 2^m
c. log2 (m)
d. 2*m
13. For the number A[15:0] =
0110110010001111, A[14:13] is ______
A[3:2].
a. less than
b. greater than
c. the same as
d . cannot be determined
14. Which of the following conditions is not
allowed in an RS latch?
a. R is asserted, S is asserted
b. R is asserted, S is negated
c. R is negated, S is asserted
d. R is negated, S is negated
15. Which of the following pair of gates
can form a latch?
a. a pair of cross coupled OR
b. a pair of cross copled AND
c. a pair of cross coupled NAND
d. a cross coupled NAND/OR
16. Who is the brain of computer:
a. ALU
b. CPU
c. MU
d. None of these
17. Which technology using the
microprocessor is fabricated on a single
chip:
a. POS
b. MOS
c. ALU
d. ABM
18. MOS stands for:
a. Metal oxide semiconductor
b. Memory oxide semiconductor
c. Metal oxide select
d. None of these
19. In which form CPU provide output:
a. Computer signals
b. Digital signals
c. Metal signals
d. None of these
20. Which is the microprocessor
comprises:
a. Register section
b. One or more ALU
c. Control unit
d. All of these
21. The register section is related
to______ of the computer:
a. Processing
b. ALU
c. Main memory
d. None of these
22. What is the store by register:
a. data
b. operands
c. memory
d. None of these
23. How many types of classification of
processor based on register section:
a. 1
b. 2
c. 3
d. 4
24. In Microprocessor one of the operands
holds a special register called:
a. Calculator
b. Dedicated
c. Accumulator
d. None of these
25. Accumulator based microprocessor
example are:
a. Intel 8085
b. Motorola 6809
c. A and B
d. None of these
26. A set of register which contain are:
a. data
b. memory addresses
c. result
d. all of these
27. How many types are primarily register:
a. 1
b. 2
c. 3
d. 4
3 | P a g e Centre for Collaboration of Industry and Institutions (CCII) – www.cmju.in
28. There are primarily two types of
register:
a. general purpose register
b. dedicated register
c. A and B
d. none of these
29. Which register is a temporary storage
location:
a. general purpose register
b. dedicated register
c. A and B
d. none of these
30. How many parts of dedicated register:
a. 2
b. 4
c. 5
d. 6
31. Name of typical dedicated register is:
a. PC
b. IR
c. SP
d. All of these
32. PC stands for:
a. Program counter
b. Points counter
c. Paragraph counter
d. Paint counter
33. IR stands for:
a. Intel register
b. In counter register
c. Index register
d. Instruction register
34. SP stands for:
a. Status pointer
b. Stack pointer
c. a and b
d. None of these
35. The act of acquiring an instruction is
referred as the____ the instruction:
a. Fetching
b. Fetch cycle
c. Both a and b
d. None of these
36. How many bit of instruction on our
simple computer consist of one____:
a. 2-bit
b. 6-bit
c. 12-bit
d. None of these
37. How many parts of single address
computer instruction :
a. 1
b. 2
c. 3
d. 4
38. Single address computer instruction
has two parts:
a. The operation code
b. The operand
c. A and B
d. None of these
39. LA stands for:
a. Load accumulator
b. Least accumulator
c. Last accumulator
d. None of these
40. ED stands for:
a. Enable MRD
b. Enable MDR
c. Both a and b
d. None of these
41. LM stands for:
a. Least MAR
b. Load MAR
c. Least MRA
d. Load MRA
42. Causing a flag to became 0 is called:
a. Clearing a flag
b. Case a flag
c. Both a and b
d. None of these
43. ____ causes the address of the next
microprocessor to be obtained from the
memory:
a. CRJA
b. ROM
c. MAP
d. HLT
44. _________ Stores the instruction
currently being executed:
a. Instruction register
b. Current register
c. Both a and b
d. None of these
4 | P a g e Centre for Collaboration of Industry and Institutions (CCII) – www.cmju.in
45. In which register instruction is
decoded prepared and ultimately executed:
a. Instruction register
b. Current register
c. Both a and b
d. None of these
46. The status register is also called
the____:
a. Condition code register
b. Flag register
c. A and B
d. None of these
47. BCD stands for:
a. Binary coded decimal
b. Binary coded decoded
c. Both a & b
d. none of these
48. Which is used to store critical pieces of
data during subroutines and interrupts:
a. Stack
b. Queue
c. Accumulator
d. Data register
49. The area of memory with addresses
near zero are called:
a. High memory
b. Mid memory
c. Memory
d. Low memory
50. The point where control returns after a
subprogram is completed is known as the :
a. Return address
b. Main Address
c. Program Address
d. Current Address
51. The subprogram finish the return
instruction recovers the return address
from the:
a. Queue
b. Stack
c. Program counter
d. Pointer
52. The processor uses the stack to keep
track of where the items are stored on it
this by using the:
a. Stack pointer register
b. Queue pointer register
c. Both a & b
d. None of these
53. Which point to the ___ of the stack:
a. TOP
b. START
c. MID
d. None of these
54. Stack words on:
a. LILO
b. LIFO
c. FIFO
d. None of these
55. Which is the basic stack operation:
a. PUSH
b. POP
c. BOTH A and B
d. None of these
56. SP stand for:
a. Stack pointer
b. Stack pop
c. Stack push
d. None of these
57. How many bit stored by status
register:
a. 1 bit
b. 4 bit
c. 6 bit
d. 8 bit
58. Which is the important part of a
combinational logic block:
a. Index register
b. Barrel shifter
c. Both a & b
d. None of these
59. The structure of the stack is _______
type structure:
a. First in last out
b. Last in last out
c. Both a & b
d. None of these
60. The data in the stack is called:
a. Pushing data
b. Pushed
c. Pulling
d. None of these
61. The CU is designed by using which
techniques:
a. Hardwired controls
b. Microprograming
c. Nanoprograming
d. All of these
5 | P a g e Centre for Collaboration of Industry and Institutions (CCII) – www.cmju.in
62. The 16 bit register is separated into
groups of 4 bit where each groups is
called:
a. BCD
b. Nibble
c. Half byte
d. None of these
63. A nibble can be represented in the from
of:
a. Octal digit
b. Decimal
c. Hexadecimal
d. None of these
64. The left side of any binary number is
called:
a. Least significant digit
b. Most significant digit
c. Medium significant digit
d. Low significant digit
65. MSD stands for:
a. Least significant digit
b. Most significant digit
c. Medium significant digit
d. Low significant digit
66. _____ a subsystem that transfer data
between computer components inside a
computer or between computer:
a. Chip
b. Register
c. Processor
d. Bus
67. Which is called superhighway:
a. Processor
b. Multiplexer
c. Backbone bus
d. None of these
68. The external system bus architecture is
created using from ______ architecture:
a. Pascal
b. Dennis Ritchie
c. Charles Babbage
d. Von Neumann
69. The network of wires or electronic path
ways on mother board back side:
a. PCB
b. BUS
c. BOTH A and B
d. None of these
70. Which Bus connects CPU & level 2
cache:
a. Rear side bus
b. Front side bus
c. Memory side bus
d. None of these
Question Booklet Code: C Duration: 2 Hours
Course: Diploma Engineering in Computer Science Year: Third Year
Paper Code: 702305 Paper Name: Microprocessor
Attempt all below mentioned questions:
1. The minimum number of transistors
required to implement a two input AND
gate is
a. 2
b. 4
c. 6
d. 8
2. Using DeMorgan's Theorem we can
convert any AND-OR structure into
a. NAND-NAND
b. OR-NAND
c. NAND-NOR
d. NOR-NAND
3. For a memory with a 16-bit address
space, the addressability is
a. 16 bits
b. 8 bits
c. 2^16 bits
d. Cannot be determined
4. Because we wish to allow each ASCII
code to occupy one location in memory,
most memories are _____ addressable.
a. BYTE
b. NIBBLE
c. WORD (16 bits)
d. DOUBLEWORD (32 bits)
5. Circuit A is a 1-bit adder; circuit B is a 1
bit multiplier.
a. Circuit A has more gates than circuit B
b. Circuit B has more gates than circuit A
c. Circuit A has the same number of gates as
circuit B
d. None of the above
6. When the write enable input is not
asserted, the gated D latch ______ its
output.
a. can not change
b. clears
c. sets
d. complements
7. A structure that stores a number of bits
taken "together as a unit" is a
a. gate
b. mux
c. decoder
d. register
8. We say that a set of gates is logically
complete if we can build any circuit
without using any other kind of gates.
Which of the following sets are logically
complete
a. set of {AND,OR}
b. set of {EXOR, NOT}
c. set of {AND,OR,NOT}
d. None of the above
9. Of the following circuits, the one which
involves storage is
a. RS Latch
b. mux
c. nand
d. decoder
10. If the number of address bits in a
memory is reduced by 2 and the
addressability is doubled, the size of the
memory (i.e., the number of bits stored in
the memory)
a. doubles
b. remains unchanged
c. halves
d. increases by 2^(address bits)/addressability
CMJ UNIVERSITY, SHILLONG
TERM END EXAMINATION - 2013
2 | P a g e Centre for Collaboration of Industry and Institutions (CCII) – www.cmju.in
11. When memory read or I/O read are
active data is to the processor:
a. Input
b. Output
c. Processor
d. None of these
12. If m is a power of 2, the number of
select lines required for an m-input mux is:
a. m
b. 2^m
c. log2 (m)
d. 2*m
13. For the number A[15:0] =
0110110010001111, A[14:13] is ______
A[3:2].
a. less than
b. greater than
c. the same as
d . cannot be determined
14. Which of the following conditions is not
allowed in an RS latch?
a. R is asserted, S is asserted
b. R is asserted, S is negated
c. R is negated, S is asserted
d. R is negated, S is negated
15. Which of the following pair of gates
can form a latch?
a. a pair of cross coupled OR
b. a pair of cross copled AND
c. a pair of cross coupled NAND
d. a cross coupled NAND/OR
16. Who is the brain of computer:
a. ALU
b. CPU
c. MU
d. None of these
17. Which technology using the
microprocessor is fabricated on a single
chip:
a. POS
b. MOS
c. ALU
d. ABM
18. MOS stands for:
a. Metal oxide semiconductor
b. Memory oxide semiconductor
c. Metal oxide select
d. None of these
19. In which form CPU provide output:
a. Computer signals
b. Digital signals
c. Metal signals
d. None of these
20. Which is the microprocessor
comprises:
a. Register section
b. One or more ALU
c. Control unit
d. All of these
21. The register section is related
to______ of the computer:
a. Processing
b. ALU
c. Main memory
d. None of these
22. What is the store by register:
a. data
b. operands
c. memory
d. None of these
23. How many types of classification of
processor based on register section:
a. 1
b. 2
c. 3
d. 4
24. In Microprocessor one of the operands
holds a special register called:
a. Calculator
b. Dedicated
c. Accumulator
d. None of these
25. Accumulator based microprocessor
example are:
a. Intel 8085
b. Motorola 6809
c. A and B
d. None of these
26. A set of register which contain are:
a. data
b. memory addresses
c. result
d. all of these
27. How many types are primarily register:
a. 1
b. 2
c. 3
d. 4
3 | P a g e Centre for Collaboration of Industry and Institutions (CCII) – www.cmju.in
28. There are primarily two types of
register:
a. general purpose register
b. dedicated register
c. A and B
d. none of these
29. Which register is a temporary storage
location:
a. general purpose register
b. dedicated register
c. A and B
d. none of these
30. How many parts of dedicated register:
a. 2
b. 4
c. 5
d. 6
31. Name of typical dedicated register is:
a. PC
b. IR
c. SP
d. All of these
32. PC stands for:
a. Program counter
b. Points counter
c. Paragraph counter
d. Paint counter
33. IR stands for:
a. Intel register
b. In counter register
c. Index register
d. Instruction register
34. SP stands for:
a. Status pointer
b. Stack pointer
c. a and b
d. None of these
35. The act of acquiring an instruction is
referred as the____ the instruction:
a. Fetching
b. Fetch cycle
c. Both a and b
d. None of these
36. How many bit of instruction on our
simple computer consist of one____:
a. 2-bit
b. 6-bit
c. 12-bit
d. None of these
37. How many parts of single address
computer instruction :
a. 1
b. 2
c. 3
d. 4
38. Single address computer instruction
has two parts:
a. The operation code
b. The operand
c. A and B
d. None of these
39. LA stands for:
a. Load accumulator
b. Least accumulator
c. Last accumulator
d. None of these
40. ED stands for:
a. Enable MRD
b. Enable MDR
c. Both a and b
d. None of these
41. LM stands for:
a. Least MAR
b. Load MAR
c. Least MRA
d. Load MRA
42. Causing a flag to became 0 is called:
a. Clearing a flag
b. Case a flag
c. Both a and b
d. None of these
43. ____ causes the address of the next
microprocessor to be obtained from the
memory:
a. CRJA
b. ROM
c. MAP
d. HLT
44. _________ Stores the instruction
currently being executed:
a. Instruction register
b. Current register
c. Both a and b
d. None of these
4 | P a g e Centre for Collaboration of Industry and Institutions (CCII) – www.cmju.in
45. In which register instruction is
decoded prepared and ultimately executed:
a. Instruction register
b. Current register
c. Both a and b
d. None of these
46. The status register is also called
the____:
a. Condition code register
b. Flag register
c. A and B
d. None of these
47. BCD stands for:
a. Binary coded decimal
b. Binary coded decoded
c. Both a & b
d. none of these
48. Which is used to store critical pieces of
data during subroutines and interrupts:
a. Stack
b. Queue
c. Accumulator
d. Data register
49. The area of memory with addresses
near zero are called:
a. High memory
b. Mid memory
c. Memory
d. Low memory
50. The point where control returns after a
subprogram is completed is known as the :
a. Return address
b. Main Address
c. Program Address
d. Current Address
51. The subprogram finish the return
instruction recovers the return address
from the:
a. Queue
b. Stack
c. Program counter
d. Pointer
52. The processor uses the stack to keep
track of where the items are stored on it
this by using the:
a. Stack pointer register
b. Queue pointer register
c. Both a & b
d. None of these
53. Which point to the ___ of the stack:
a. TOP
b. START
c. MID
d. None of these
54. Stack words on:
a. LILO
b. LIFO
c. FIFO
d. None of these
55. Which is the basic stack operation:
a. PUSH
b. POP
c. BOTH A and B
d. None of these
56. SP stand for:
a. Stack pointer
b. Stack pop
c. Stack push
d. None of these
57. How many bit stored by status
register:
a. 1 bit
b. 4 bit
c. 6 bit
d. 8 bit
58. Which is the important part of a
combinational logic block:
a. Index register
b. Barrel shifter
c. Both a & b
d. None of these
59. The structure of the stack is _______
type structure:
a. First in last out
b. Last in last out
c. Both a & b
d. None of these
60. The data in the stack is called:
a. Pushing data
b. Pushed
c. Pulling
d. None of these
61. The CU is designed by using which
techniques:
a. Hardwired controls
b. Microprograming
c. Nanoprograming
d. All of these
5 | P a g e Centre for Collaboration of Industry and Institutions (CCII) – www.cmju.in
62. The 16 bit register is separated into
groups of 4 bit where each groups is
called:
a. BCD
b. Nibble
c. Half byte
d. None of these
63. A nibble can be represented in the from
of:
a. Octal digit
b. Decimal
c. Hexadecimal
d. None of these
64. The left side of any binary number is
called:
a. Least significant digit
b. Most significant digit
c. Medium significant digit
d. Low significant digit
65. MSD stands for:
a. Least significant digit
b. Most significant digit
c. Medium significant digit
d. Low significant digit
66. _____ a subsystem that transfer data
between computer components inside a
computer or between computer:
a. Chip
b. Register
c. Processor
d. Bus
67. Which is called superhighway:
a. Processor
b. Multiplexer
c. Backbone bus
d. None of these
68. The external system bus architecture is
created using from ______ architecture:
a. Pascal
b. Dennis Ritchie
c. Charles Babbage
d. Von Neumann
69. The network of wires or electronic path
ways on mother board back side:
a. PCB
b. BUS
c. BOTH A and B
d. None of these
70. Which Bus connects CPU & level 2
cache:
a. Rear side bus
b. Front side bus
c. Memory side bus
d. None of these
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